FAILURE-RESISTANT SYSTEMS

Post Date

April 24th 2012

Application Due Date

July 26th 2012

Full Proposal Deadline(s): July 26, 2012

Funding Opportunity Number

12-556

CFDA Number(s)

47.041
47.070

Funding Instrument Type(s)

Grant

Funding Activity Categories

Science and Technology and other Research and Development

Number of Awards

20

Eligibility Categories

Other

*Organization Limit: Proposals may only be submitted by the following: -Universities and Colleges - Universities and two- and four-year colleges (including community colleges) accredited in, and having a campus located in the US, acting on behalf of their faculty members. Such organizations also are referred to as academic institutions.

Funding

• Estimated Total Funding:

  $6000000

• Award Range:

  $300000 - $400000

Grant Description

The National Science Foundation (NSF) and the Semiconductor Research Corporation (SRC) have agreed to embark on a new collaborative research program to address compelling research challenges in failure resistant systems that are of paramount importance to industry, academia, and society at large.New approaches in the design of electronic circuits and systems are needed for products and services that continue to operate correctly in the presence of transient, permanent, or systematic failures. From large information processing systems supporting communications and computation, to small embedded systems targeting medical and automotive applications, whole industries are facing the challenge of improving the reliability of systems. Increasing miniaturization and integrated circuit fabrication processes are creating a tension between reliability and efficiency. Higher rates of faults, variation, and degradation due to aging in integrated circuits are forcing systems engineers to assume that devices and circuits may not always perform as designed. More and more, systems are constructed using IP blocks (3rd party Intellectual Property) from different sources, contributing further to unpredictable behavior. ??Thus behavior under adverse conditions may not be fully known in deployed systems. Current techniques for ensuring reliability, such as voltage and clock rate margins, replication, and disk-based check-pointing will not be able to satisfy the competing requirements for future integrated circuits. These techniques typically operate only at one level of the system stack, yet layers from devices to applications all contribute to system reliability. Such single-layer techniques must be used under worst-case assumptions about the other layers in the stack.?? This potentially leads to inefficiencies that will make these techniques impractical in future fabrication processes. A system-level cross-layer approach to reliability, encompassing failure mechanisms of both digital and analog components, has the potential to deliver high reliability with significantly lower power and performance overheads than current single-layer techniques. By distributing reliability across the system design stack, cross-layer approaches can take advantage of the information available at each level, including even application-level knowledge, to efficiently tolerate errors, aging, and variation. This will allow handling of different physical effects at the most efficient stack layer, and can be adapted to varying application needs, operating environments, and changing hardware state. Fundamental new advances in techniques for designing and developing systems resilient to failure could have a significant impact on multiple industries and boost their competitiveness on a global scale, helping to transform market segments and translate research results into practice.

Contact Information

• Agency

  National Science Foundation

• Office:

  None

• Agency Contact:

  NSF grants.gov support
  grantsgovsupport@nsf.gov
  

• Agency Mailing Address:

  If you have any problems linking to this funding announcement, please contact

• Agency Email Address:

  grantsgovsupport@nsf.gov

• More Information:

  NSF Publication 12-556